Functional simulation in the lamp system
DAC '76 Proceedings of the 13th Design Automation Conference
Serial/parallel event scheduling for the simulation of large systems
ACM '68 Proceedings of the 1968 23rd ACM national conference
DAC '74 Proceedings of the 11th Design Automation Workshop
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
Design and verification of large-scale computers by using DDL
DAC '79 Proceedings of the 16th Design Automation Conference
Logic verification system for very large computers using LSI's
DAC '79 Proceedings of the 16th Design Automation Conference
A microarchitecture description language for retargeting firmware tools
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
A dynamic very high-level debugger for low-level microprograms
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
HAL; A block level hardware logic simulator
25 years of DAC Papers on Twenty-five years of electronic design automation
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Structured design verification: Function and timing
DAC '83 Proceedings of the 20th Design Automation Conference
MDS: An improved total system for firmware development
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Design automation status in Japan
DAC '81 Proceedings of the 18th Design Automation Conference
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A CAD system for logic design based on frames and demons
DAC '81 Proceedings of the 18th Design Automation Conference
An Interactive Simulation System for structured logic design—ISS
DAC '82 Proceedings of the 19th Design Automation Conference
Logic design verification using automated test generation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities. Main MIXS techniques are time wheel and selective trace algorithm for functional level simulation based on 'node' model concept and the linkage function of functional models, described in different detail, with network information. The mixed level simulation for large digital systems can be achieved very efficiently by using the above techniques.