Logic design verification using automated test generation

Authors:
Tohru Sasaki;Shunichi Kato;Nobuyoshi Nomizu;Hidetoshi Tanaka
Affiliations:
NEC Corporation, Fuchu City, Tokyo, Japan;NEC Corporation, Fuchu City, Tokyo, Japan;NEC Corporation, Fuchu City, Tokyo, Japan;NEC Corporation, Fuchu City, Tokyo, Japan
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence. This new approach has been developed as a function of a mixed level simulator, MIXS1, and has strengthened MIXS top-down and bottom-up design support capabilities.