HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Logic verification system for very large computers using LSI's
DAC '79 Proceedings of the 16th Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An extensive logic simulation method of very large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Optimizing VHDL Compilation for Parallel Simulation
IEEE Design & Test
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This paper describes new simulation which reduce the computing requirement of a gate level logic simulator. The logic circuit to be simulated is transformed into the smaller one. The number of events as well as the storage necessary for expressing the logic circuits are decreased. Also, the evaluation of gates becomes faster by predicting whether a gate's input signal change would cause the gate's output signal change or not. Our simulator with these techniques has dealt with the logic of some 1,200,000 gates and has saved the computer processing time in developing our computer products.