Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimizing VHDL compilation for parallel simulation
Optimizing VHDL compilation for parallel simulation
Speed up techniques of logic simulation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Program Flow Analysis: Theory and Application
Program Flow Analysis: Theory and Application
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
A mathematical theory of global program optimization (Prentice-Hall series in automatic computation)
A mathematical theory of global program optimization (Prentice-Hall series in automatic computation)
An evaluation system for distributed-time VHDL simulation
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
EURO-DAC '94 Proceedings of the conference on European design automation
Use of embedded scheduling to compile VHDL for effective parallel simulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Concurrency-aware compiler optimizations for hardware description languages
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Auriga, an experimental simulator that utilizes five compilation techniques to reduce runtime complexity and promote concurrency in the simulation of VHDL models is described. Auriga is designed to translate a model using any VHDL construct into an optimized, parallel simulation. Auriga's distributed simulation uses a message-passing network to simulate a single VHDL model. The authors present results obtained with seven benchmark models to illustrate the compiler's aggressive optimization techniques: temporal analysis, waveform propagation, input desensitization, concurrent evaluation, and statement compaction.