An evaluation system for distributed-time VHDL simulation

Authors:
Alessandra Costa;Alessandro de Gloria;Paolo Faraboschi;Mauro Olivieri
Affiliations:
University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy;University of Genoa - DIBE, Via Opera Pia 1la, 16145 Genova, Italy;University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy;University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Venue:
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Year:
1994

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Abstract

Performance of VHDL simulation is a critical issue in electronic circuit design and is hard to achieve due to the complexity of the language and the different abstraction levels.This paper presents a system for performance evaluation of distributed-time VHDL simulation based on the analysis of simulation traces. The system allows to model different architectures, interconnection topologies and simulation algorithms. The main tools are a VHDL analyzer to extract dependencies, and a trace-driven simulator to evaluate the execution time on a given architecture.