Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
LECSIM: a levelized event driven compiled logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A general method for compiling event-driven simulations
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Parallel compiled event driven VHDL simulation
ICS '98 Proceedings of the 12th international conference on Supercomputing
Hardware logic simulation by compilation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Data Flow Analysis for Procedural Languages
Journal of the ACM (JACM)
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
Optimizing VHDL Compilation for Parallel Simulation
IEEE Design & Test
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article, we discuss the application of compiler technology for eliminating redundant computation in hardware simulation. We discuss how concurrency in hardware description languages (HDLs) presents opportunities for expression reuse across different threads. While accounting for discrete event simulation semantics, we extend the data flow analysis framework to concurrent threads. In this process, we introduce a rewriting scheme named ∂VF and a graph representation to model sensitivity relationships among threads. An algorithm for identifying common subexpressions as applied to HDLs is presented. Related issues, such as scheduling correctness, are also considered.