Parallel compiled event driven VHDL simulation

An improved cost function for static partitioning of parallel circuit simulations using a conservative synchronization protocol

PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation

A general method for compiling event-driven simulations

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Actor based parallel VHDL simulation using time warp

PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation

Logic synthesis using Synopsys (2nd ed.)

Logic synthesis using Synopsys (2nd ed.)

Parallel algorithms for VHDL simulation

Parallel algorithms for VHDL simulation

Implications of VHDL timing models on simulation and software synthesis

Journal of Systems Architecture: the EUROMICRO Journal

Ravel: assigned-delay compiled-code logic simulation

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits

Load Balancing and Workload Minimization Of Overlapping Parallel Tasks

ICPP '97 Proceedings of the international Conference on Parallel Processing

Parallel processing for vlsi simulation

Parallel processing for vlsi simulation