ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Parallelism extraction and program restructuring for parallel simulation of digital systems
Parallelism extraction and program restructuring for parallel simulation of digital systems
A unified framework for conservative and optimistic distributed simulation
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel compiled event driven VHDL simulation
ICS '98 Proceedings of the 12th international conference on Supercomputing
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
The dependence list in time warp
Proceedings of the fifteenth workshop on Parallel and distributed simulation
A causality based time management mechanism for federated simulation
Proceedings of the fifteenth workshop on Parallel and distributed simulation
Parallel simulation: parallel and distributed simulation systems
Proceedings of the 33nd conference on Winter simulation
Automatic Parallelization of Compiled Event Driven VHDL Simulation
IEEE Transactions on Computers
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ErrorTracer: design error diagnosis based on fault simulation techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Observability Analysis on HDL Descriptions for Effective Functional Validation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article proposes a new algorithm for parallel synchronous simulation of VHDL designs to be executed on desktop computers. Besides executing VHDL processes in parallel, the algorithm focuses on parallelizing the simulation kernel with special emphasis on signal grouping while maintaining language semantics. Synchronous approaches are the most suitable for shared memory multiprocessor (SMP) desktop computers but may be difficult to parallelize because of the low activity detected in most of the designs. The degree of parallelism is increased in this approach by performing an exhaustive VHDL signal dependencies analysis and avoiding any sequential phase in the simulator. VHDL semantics impose a synchronization barrier after each phase, that is, the process and the kernel simulation phase, as the language definition does not allow simultaneous execution of kernel and processes. These barriers have been relaxed in order to increase the level of parallelism and obtain better performance. Another aspect the new algorithm takes into account is to improve load balancing and locality of references, both critical issues in synchronous simulators, by introducing a new load balancing algorithm that exploits the cyclic characteristics of circuit simulators. These developments make the algorithm suitable for commodity hardware, that is, SMP that are currently used as desktop personal computers.