Communicating sequential processes
Communicating sequential processes
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
Statecharts: A visual formalism for complex systems
Science of Computer Programming
LUSTRE: a declarative language for real-time programming
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Modern operating systems
Asynchronous algorithms for the parallel simulation of event-driven dynamical systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Mechanized reasoning and hardware design
Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
A general method for compiling event-driven simulations
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The STATEMATE semantics of statecharts
ACM Transactions on Software Engineering and Methodology (TOSEM)
Bounded scheduling of process networks
Bounded scheduling of process networks
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Scheduling hardware/software systems using symbolic techniques
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Synthesis of embedded software using free-choice Petri nets
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Software Engineering
Derivatives of Regular Expressions
Journal of the ACM (JACM)
Squeak: a language for communicating with mice
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Software synthesis from statechart models for real time systems
DIPES '98 Proceedings of the IFIP WG10.3/WG10.5 international workshop on Distributed and parallel embedded systems
Compiling Esterel into sequential code
Proceedings of the 37th Annual Design Automation Conference
Task generation and compile-time scheduling for mixed data-control embedded software
Proceedings of the 37th Annual Design Automation Conference
Efficient compilation of ESTEREL for real-time embedded systems
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Exclusive simulation of activity in digital networks
Communications of the ACM
Efficient compilation of process-based concurrent programs without run-time scheduling
Proceedings of the conference on Design, automation and test in Europe
Microc/OS-II
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Meeting Deadlines in Hard Real-Time Systems
Meeting Deadlines in Hard Real-Time Systems
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Operating System Concepts, 4th Ed.
Operating System Concepts, 4th Ed.
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
The ESTEREL Synchronous Programming Language and its Mathematical Semantics
Seminar on Concurrency, Carnegie-Mellon University
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
ACM '65 Proceedings of the 1965 20th national conference
Compositional Software Synthesis of Communicating Processes
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Modular Domain Specific Languages and Tools
ICSR '98 Proceedings of the 5th International Conference on Software Reuse
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Synthesis of software programs for embedded control applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generating fast code from concurrent program dependence graphs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Causality analysis of synchronous programs with delayed actions
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Code partitioning for synthesis of embedded applications with phantom
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient code generation from SHIM models
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Mapping esterel onto a multi-threaded embedded processor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Synthesis of time-constrained multitasking embedded software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HW/SW co-design for Esterel processing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Worst Case Reaction Time Analysis of Concurrent Reactive Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
A rigorous approach towards test case generation
Information Sciences: an International Journal
Code decomposition and recomposition for enhancing embedded software performance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Compiling Esterel into Static Discrete-Event Code
Electronic Notes in Theoretical Computer Science (ENTCS)
Separate compilation for synchronous modules
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Concurrency-aware compiler optimizations for hardware description languages
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Embedded systems often include a traditional processor capable of executing sequential code, but both control and data-dominated tasks are often more naturally expressed using one of the many domain-specific concurrent specification languages. This article surveys a variety of techniques for translating these concurrent specifications into sequential code. The techniques address compiling a wide variety of languages, ranging from dataflow to Petri nets. Each uses a different method, to some degree chosen to match the semantics of concurrent language. Each technique is considered to consist of a partial evaluator operating on an interpreter. This combination provides a clearer picture of how parts of each technique could be used in a different setting.