On the development of reactive systems
Logics and models of concurrent systems
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Static Worst-Case Execution Time Analysis of Synchronous Programs
Ada-Europe '00 Proceedings of the 5th Ada-Europe International Conference on Reliable Software Technologies
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Towards direct execution of esterel programs on reactive processors
Proceedings of the 4th ACM international conference on Embedded software
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Esterel processor with full preemption support and its worst case reaction time analysis
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Optimization for faster execution of Esterel programs
Formal methods and models for system design
A concurrent reactive Esterel processor based on multi-threading
Proceedings of the 2006 ACM symposium on Applied computing
Mapping esterel onto a multi-threaded embedded processor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Instantaneous termination in pure Esterel
SAS'03 Proceedings of the 10th international conference on Static analysis
Predicting computation time for advanced processor architectures
Euromicro-RTS'00 Proceedings of the 12th Euromicro conference on Real-time systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance debugging of Esterel specifications
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Tight WCRT analysis of synchronous C programs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Context-sensitive timing analysis of Esterel programs
Proceedings of the 46th Annual Design Automation Conference
Reactive parallel processing for synchronous dataflow
Proceedings of the 2010 ACM Symposium on Applied Computing
Timing analysis of esterel programs on general-purpose multiprocessors
Proceedings of the 47th Design Automation Conference
WCRT algebra and interfaces for Esterel-style synchronous processing
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient WCRT analysis of synchronous programs using reachability
Proceedings of the 48th Design Automation Conference
Timing analysis enhancement for synchronous program
Proceedings of the 21st International conference on Real-Time Networks and Systems
ILPc: a novel approach for scalable timing analysis of synchronous programs
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Hi-index | 0.00 |
Reactive programs have to react continuously to their inputs. Here the time needed to react with the according output is important. While the synchrony hypothesis takes the view that the program is infinitely fast, real computations take time. Similar to the traditional Worst Case Execution Time (WCET), the Worst Case Reaction Time (WCRT) of a program determines the maximal time for one reaction. In this paper, we present an algorithm to determine the WCRT of a program written in the synchronous language Esterel. This value gives an upper bound for the execution time when the program is executed on a reactive processor. Specifically, we consider the execution of the Esterel program on the Kiel Esterel Processor (KEP), a reactive processor that can execute Esterel-like instructions. Here the WCRT directly determines an upper bound on the instruction cycles per logical tick. The WCRT also gives a guideline for the execution time when the Esterel program is compiled to software by a simulation-based approach. We have implemented the WCRT analysis algorithm as part of an Esterel compiler for the Kiel Esterel Processor (KEP) and have measured an accuracy of analysis results of about 22% on average.