Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Worst Case Reaction Time Analysis of Concurrent Reactive Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Performance debugging of Esterel specifications
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Compiling Esterel
Context-sensitive timing analysis of Esterel programs
Proceedings of the 46th Annual Design Automation Conference
WCRT algebra and interfaces for Esterel-style synchronous processing
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient WCRT analysis of synchronous programs using reachability
Proceedings of the 48th Design Automation Conference
Passive code in synchronous programs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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Synchronous languages like Esterel have gained wide popularity in certain domains such as avionics. However, platform-specific timing analysis of code generated from Esterel-like specifications have mostly been neglected so far. The growing volume of electronics and software in domains like automotive, calls for formal-specification based code generation to replace manually written and optimized code. Such cost-sensitive domains require tight estimation of timing properties of the generated code. Towards this goal, we propose a scheme for generating C code from Esterel specifications for a multiprocessor platform, followed by timing analysis of the generated code. Due to dependencies across program fragments mapped onto different processors, traditional Worst-Case Execution Time (WCET) analysis techniques for sequential programs cannot applied be to this setting. Our proposed timing analysis technique is tailored to capture such inter-processor code dependencies. Our main novelty stems from how we detect and remove infeasible paths arising from a multiprocessor implementation during our timing analysis. We apply our timing analysis on a number of standard Esterel benchmarks, which show that performing the proposed inter-processor infeasible path elimination may lead to up to 14.3% tighter estimation of the WCRT, thereby leading to resource over-dimensioning and poor design.