Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A fast mutual exclusion algorithm
ACM Transactions on Computer Systems (TOCS)
Calculating the maximum, execution time of real-time programs
Real-Time Systems
The STATEMATE semantics of statecharts
ACM Transactions on Software Engineering and Methodology (TOSEM)
ECL: a specification environment for system-level design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cache miss equations: a compiler framework for analyzing and tuning memory behavior
ACM Transactions on Programming Languages and Systems (TOPLAS)
Proof, language, and interaction
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Digital Design with VERILOG HDL
Digital Design with VERILOG HDL
Proving the Equivalence of Microstep and Macrostep Semantics
TPHOLs '02 Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
Automatic Accurate Time-Bound Analysis for High-Level Languages
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Verified Hardware Synthesis of Esterel Programs
DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
Introducing Mutual Exclusion in Esterel
PSI '99 Proceedings of the Third International Andrei Ershov Memorial Conference on Perspectives of System Informatics
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Modeling VHDL in Multiclock ESTEREL
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Multiclock Esterel: A Reactive Framework for Asynchronous Design
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
A New Approach to the Specification and Verification of Real-Time Systems
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Extending Synchronous Languages for Generating Abstract Real-Time Models
Proceedings of the conference on Design, automation and test in Europe
Symbolic Model Checking of Real-Time Systems
TIME '01 Proceedings of the Eighth International Symposium on Temporal Representation and Reasoning (TIME'01)
Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Towards validated real-time software
Euromicro-RTS'00 Proceedings of the 12th Euromicro conference on Real-time systems
Performance debugging of Esterel specifications
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Tight WCRT analysis of synchronous C programs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Context-sensitive timing analysis of Esterel programs
Proceedings of the 46th Annual Design Automation Conference
Timing analysis of esterel programs on general-purpose multiprocessors
Proceedings of the 47th Design Automation Conference
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Synchronous programming languages are well-suited forthe implementation and verification of real-time systems.The main benefit for the estimation of real-time constraintsis thereby that the macro steps provided by synchronousprograms can be directly used for runtime analysis: If synchronouscircuits are generated from these descriptions, themacro steps are implemented by combinatorial circuits, andif software is generated, they correspond to basic buildingblocks that do not contain loops. In this paper, we describemethods to generate timed transitions systems froma synchronous program by taking the final architecture intoaccount. For software synthesis, this requires to considerdifferent microprocessors and compilers, and for hardwaresynthesis, this requires to consider a hierarchy of clocks tooptimize the clock speed.