Hardware logic simulation by compilation

  • Authors:
  • Craig Hansen

  • Affiliations:
  • MIPS Computer Systems, Inc., 930 Arques Avenue, Sunnyvale, CA

  • Venue:
  • DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
  • Year:
  • 1988

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Abstract

A behavioral and logic simulation system which uses extensive optimization and compilation techniques to obtain high performance is described. It incorporates data flow analysis to optimize the evaluation of unordered assignment statement that define a hardware structure, and extract clocking rules. An integral code generator produces efficient assembly code for three different machines, and an associated run-time library provides a flexible interactive debugging environment.