Mesh routing topologies for multi-FPGA systems

Authors:
Scott Hauck;Gaetano Borriello;Carl Ebeling
Affiliations:
Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL;Department of Computer Science and Engineering, University of Washington, Seattle, WA;Department of Computer Science and Engineering, University of Washington, Seattle, WA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1998

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Abstract

There is currently great interest in using fixed arrays of FPGA's for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGA's. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh.