Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing Driven Multi-FPGA Board Partitioning
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.