TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation

Authors:
Charles Selvidge;Anant Agarwal;Matt Dahl;Jonathan Babb
Affiliations:
Virtual Machine Works, Inc., 1 Kendall Sq. Building 300, Cambridge, MA;Virtual Machine Works, Inc., 1 Kendall Sq. Building 300, Cambridge, MA;Virtual Machine Works, Inc., 1 Kendall Sq. Building 300, Cambridge, MA;Virtual Machine Works, Inc., 1 Kendall Sq. Building 300, Cambridge, MA
Venue:
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Year:
1995

Citing 2
Cited 8

Data networks

Data networks
Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors

IEEE Micro

Static schedluing of multiple asynchronous domains for functional verification

Proceedings of the 38th annual Design Automation Conference
Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
Logic emulation with virtual wires

Readings in hardware/software co-design
Automated design synthesis and partitioning for adaptive reconfigurable hardware

Hardware implementation of intelligent systems
Static scheduling of multi-domain memories for functional verification

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Baring It All to Software: Raw Machines

Computer
Mesh routing topologies for multi-FPGA systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging latency-insensitivity to ease multiple FPGA design

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

TIERS is a new pipelined routing and scheduling algorithm implemented in a complete VirtualWireTM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.