Leveraging latency-insensitivity to ease multiple FPGA design

Authors:
Kermin Elliott Fleming;Michael Adler;Michael Pellauer;Angshuman Parashar;Arvind Mithal;Joel Emer
Affiliations:
MIT, Cambridge, MA, USA;Intel, Hudson, MA, USA;MIT, Hudson, MA, USA;Intel, Hudson, MA, USA;MIT, Cambridge, MA, USA;MIT, Cambridge, MA, USA
Venue:
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Year:
2012

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Abstract

Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance.