Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis of operation-centric hardware descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
The FAST methodology for high-speed SoC/computer simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs
ISPASS '08 Proceedings of the ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operation-centric hardware description and synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
From plasma to beefarm: design experience of an FPGA-based multicore prototype
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Leveraging latency-insensitivity to ease multiple FPGA design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Automatic generation of hardware/software interfaces
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Resource-bounded multicore emulation using Beefarm
Microprocessors & Microsystems
Hi-index | 0.01 |
We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.