Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Using partitioning to help convergence in the standard-cell design automation methodology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
BONeS DESIGNER: A Graphical Environment for Discrete-Event Modeling and Simulation
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
A formal approach to designing delay-insensitive circuits
Distributed Computing
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Coping with Latency in SOC Design
IEEE Micro
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
Issues in Implementing Latency Insensitive Protocols
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2004 international symposium on Physical design
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New System Design Methodology for Wire Pipelined SoC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Formal Methods in System Design
Validating Families of Latency Insensitive Protocols
IEEE Transactions on Computers
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A general model for performance optimization of sequential systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Distributed flit-buffer flow control for networks-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Performance optimization of elastic systems using buffer resizing and buffer insertion
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Another Glance at Relay Stations in Latency-Insensitive Design
Electronic Notes in Theoretical Computer Science (ENTCS)
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
A Functional Programming Framework for Latency Insensitive Protocol Validation
Electronic Notes in Theoretical Computer Science (ENTCS)
Bounded dataflow networks and latency-insensitive circuits
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-clock SoC design using protocol conversion
Proceedings of the Conference on Design, Automation and Test in Europe
Logical time: specification vs. implementation
ACM SIGSOFT Software Engineering Notes
Throughput optimization for latency-insensitive system with minimal queue insertion
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Critical systems development methodology using formal techniques
Proceedings of the Third Symposium on Information and Communication Technology
Correct-by-construction multi-component SoC design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
| Hi-index | 0.00 |
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionaly equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.