Communicating sequential processes
Communicating sequential processes
Trace theory and systolic computations
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
The translation of processes into circuits
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
Concurrent computations and VLSI circuits
Control Flow and Data Flow: concepts of distributed programming
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Communications of the ACM
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Communicating sequential processes
Communications of the ACM
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to VLSI Systems
Networks of Communicating Processes and Their (De-)Composition
Proceedings of the International Conference on Mathematics of Program Construction, 375th Anniversary of the Groningen University
Relative Liveness: From Intuition to Automated Verification
Formal Methods in System Design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
Statistical Carry Lookahead Adders
IEEE Transactions on Computers
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Concurrency and Hardware Design, Advances in Petri Nets
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Relative liveness: from intuition to automated verification
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Analysis and Applications of the XDI model
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Fully asynchronous, robust, high-throughput arithmetic structures
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Concurrent computing machines and physical space-time
Mathematical Structures in Computer Science
Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor
ANSS '04 Proceedings of the 37th annual symposium on Simulation
Optimal message-driven implementations of omega with mute processes
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
Optimal message-driven implementation of omega with mute processes
SSS'06 Proceedings of the 8th international conference on Stabilization, safety, and security of distributed systems
The Asynchronous Bounded-Cycle model
Theoretical Computer Science
Relativistic Causality and Clockless Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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A method for designing delay-insensitive circuits is presented based on a simple formalism. The communication behavior of a circuit with its environment is specified by a regular expression-like program. Based on formal manipulations this program is then transformed into a delay-insensitive network of basic elements realizing the specified circuit. The notion of delay-insensitivity is concisely formalized.