A Fast 1-D Serial-Parallel Systolic Multiplier
IEEE Transactions on Computers
Serial-data computation
Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Four State Asynchronous Architectures
IEEE Transactions on Computers
Asynchronous Multipliers as Combinational Handshake Circuits
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
A formal approach to designing delay-insensitive circuits
Distributed Computing
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This paper presents some novel circuit designs for bit serial adders and multipliers built out of some unusual, but well-defined circuit primitives. The circuits are fully delay-insensitive, provide good reliability and speed, and are easily verified. The structures are flexible and handle inputs of arbitrary lengths while being asymptotically optimal in speed and area. The scaleability of these circuits makes them. Very attractive for applications such as RSA cryptosystems which need very large operands and fast multiplication.