A Fast 1-D Serial-Parallel Systolic Multiplier

Authors:
I.-C. Wu
Affiliations:
-
Venue:
IEEE Transactions on Computers
Year:
1987

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Abstract

Based on the modified Booth's algorithm, a fast 1-D serial- parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2 cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n = N) multiplier and an m-bit multiplicand is equal to n + m - 1, and independent of the circuit size N.