A Signed Bit-Sequential Multiplier
IEEE Transactions on Computers
A Fast 1-D Serial-Parallel Systolic Multiplier
IEEE Transactions on Computers
Modular exponentiation using recursive sums of residues
CRYPTO '89 Proceedings on Advances in cryptology
Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
IEEE Transactions on Computers
On a Bit-Serial Input and Bit-Serial Output Multiplier
IEEE Transactions on Computers
A Canonical Bit-Sequential Multiplier
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
Microelectronic architectures and devices for signal and symbol processing
Integration, the VLSI Journal
A real-time systolic integer multiplier
Integration, the VLSI Journal
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
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Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical circuit consisting of 2n modules, each being only slightly more complex than a full adder; instead of three inputs and two outputs, each module has five inputs and three outputs. A logical circuit realization is given for the modules. But perhaps the most significant aspect of this design is the property that the input is required only bit-sequentially and the output is generated bit-sequentially, both at the rate of one bit per time step, least significant bit first. The advantages of such bit-sequential input and output arithmetic units are described.