Introduction to VLSI Systems
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output
IEEE Transactions on Computers
A Signed Bit-Sequential Multiplier
IEEE Transactions on Computers
Modular exponentiation using recursive sums of residues
CRYPTO '89 Proceedings on Advances in cryptology
Microelectronic architectures and devices for signal and symbol processing
Integration, the VLSI Journal
A real-time systolic integer multiplier
Integration, the VLSI Journal
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A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculation of a 2k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on the number of bits in the product. The internal logic for generating the inputs to the carry-save adders is given. This cell directly accepts the bit-serial inputs and generates a bit-serial output. Longer binary operands can be multiplied by simply cascading identical cells without change to existing cells. A given multiplier can process shorter operands in correspondingly shorter times. Applicability of this technique to VLSI implementation of the basic multiply/add operation useful in signal processing algorithms is described.