Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
IEEE Transactions on Computers
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
On a Bit-Serial Input and Bit-Serial Output Multiplier
IEEE Transactions on Computers
A Canonical Bit-Sequential Multiplier
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output
IEEE Transactions on Computers
Incremental Computation of Squares and Sums of Squares
IEEE Transactions on Computers
On Serial-Input Multipliers for Two's Complement Numbers
IEEE Transactions on Computers
Bit-Serial Multipliers and Squarers
IEEE Transactions on Computers
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Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.