A Signed Bit-Sequential Multiplier
IEEE Transactions on Computers
Comments, on 'A Signed Bit-Sequential Multiplier' by T. Rhyne and N.R. Strader II
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
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An incremental algorithm for computation of sums of squares is presented that is suitable for both most-significant-bit- (MSB-)first and least-significant-bit- (LSB-)first bit-sequential operation. By exploiting symmetry properties of numerical values and evaluation times in the bit-product matrix, it is shown how incremental multipliers can be converted to perform squaring at reduced hardware cost, and sum of squaring at a hardware cost to that of scalar multiplication. By the elimination of redundant computation, existing hardware modules are either reduced in size or assigned to the evaluation of a second squaring computation. The corresponding hardware architectures are derived from a simple conversion of existing incremental scalar multipliers. This conversion process is less practical on standard serial/parallel or serial-pipeline multipliers. A digit-on-line algorithm is outlined for magnitude extraction operations on plane vectors.