On Serial-Input Multipliers for Two's Complement Numbers
IEEE Transactions on Computers
On the capabilities of systolic systems (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
The retiming lemma: a simple proof and applications
Integration, the VLSI Journal
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
Systolic Modular Multiplication
CRYPTO '90 Proceedings of the 10th Annual International Cryptology Conference on Advances in Cryptology
Real-Time Computation by n-Dimensional Iterative Arrays of Finite-State Machines
IEEE Transactions on Computers
Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
IEEE Transactions on Computers
A Canonical Bit-Sequential Multiplier
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output
IEEE Transactions on Computers
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We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a nonpipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.