Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Predicate calculus and program semantics
Predicate calculus and program semantics
Acta Informatica
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Analyzing Specifications for Delay-Insensitive Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Building Finite Automata from DI Specifications
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Process spaces and formal verification of asynchronous circuits
Process spaces and formal verification of asynchronous circuits
A formal approach to designing delay-insensitive circuits
Distributed Computing
Solution of parallel language equations for logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Concurrency and Hardware Design, Advances in Petri Nets
Concurrent computing machines and physical space-time
Mathematical Structures in Computer Science
Verification and implementation of delay-insensitive processes in restrictive environments
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Controllable Delay-Insensitive Processes
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
Controllable Delay-Insensitive Processes
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
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It is not always straightforward to implement a network that is robust enough to be functionally independent of communication delay. In order to specify and verify so called Delay Insensitive networks, numerous models and formalisms have been developed. In this paper we analyze one of the most expressive models. We show how based on rewrite rules we can compute, rather than invent parts of a network. We implemented these computations in a tool. We also show how healthiness, finite execution models and a distributive parallel composition cannot coexist.