Communicating sequential processes
Communicating sequential processes
Algebraic theory of processes
Submodule construction as equation solving in CCS
Theoretical Computer Science
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Acta Informatica
Modelling, analysis and synthesis of asynchronous control circuits using Petri nets
Integration, the VLSI Journal
Delay-insensitive interface specification and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the Construction of Submodule Specifications and Communication Protocols
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Normal Form in a Delay-Insensitive Algebra
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
A Programming Approach to the Design of Asynchronous Logic Blocks
Concurrency and Hardware Design, Advances in Petri Nets
Concurrency and Hardware Design, Advances in Petri Nets
Submodule Construction and Supervisory Control: A Generalization
CIAA '01 Revised Papers from the 6th International Conference on Implementation and Application of Automata
Normal Form in DI-Algebra with Recursion
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Analyzing Specifications for Delay-Insensitive Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Analysis and Applications of the XDI model
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification and implementation of delay-insensitive processes in restrictive environments
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
A compositional specification theory for component behaviours
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
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Josephs and Udding's DI-Algebra offers a convenient way of specifying and verifying designs that must rely upon delay-insensitive signalling between modules (asynchronous logic blocks). It is based on Hoare's theory of CSP, including the notion of refinement between processes, and is similarly underpinned by a denotational semantics. Verhoeff developed an alternative theory of delay-insensitive design based on a testing paradigm and the concept of reflection. The first contribution of this paper is to define a relation between processes in DI-Algebra that captures Verhoeff's notion of a closed system passing a test (by being free of interference and deadlock). The second contribution is to introduce a new notion of controllability, that is, to define what it means for a process to be controllable in DI-Algebra. The third contribution is to extend DI-Algebra with a reflection operator and to show how testing relates to controllability, reflection and refinement. It is also shown that double reflection yields fully-abstract processes in the sense that it removes irrelevant distinctions between controllable processes. The final contribution is a modified version of Verhoeff's factorisation theorem that could potentially be of major importance for constructive design and the development of design tools. Several elementary examples are worked out in detail to illustrate the concepts. The claims made in this paper are accompanied by formal proofs, mostly in an annotated calculational style.