Communicating sequential processes
Communicating sequential processes
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Java I/O
Delay-insensitive interface specification and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Normal Form in a Delay-Insensitive Algebra
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
An Algebra for Delay-Insensitive Circuits
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
A structural encoding technique for the synthesis of asynchronous circuits
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Building Finite Automata from DI Specifications
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Analysis of Reshuffled Handshaking Expansions
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Proceedings of the 41st annual Design Automation Conference
How to synthesize nets from languages: a survey
Proceedings of the 39th conference on Winter simulation: 40 years! The best is yet to come
Controllable Delay-Insensitive Processes
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Synthesis of Petri Nets from Finite Partial Languages
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Synthesis of Petri Nets from Term Based Representations of Infinite Partial Languages
Fundamenta Informaticae - Application of Concurrency to System Design
Synthesis of Petri Nets from Term Based Representations of Infinite Partial Languages
Fundamenta Informaticae - Application of Concurrency to System Design
Synthesis of Petri Nets from Finite Partial Languages
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Controllable Delay-Insensitive Processes
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchronous logic block is to interact with its environment. Using the tool di2pn, such a specification can be automatically translated into a Petri net. Using the tool petrify, the net can be automatically validated (for freedom from deadlock and interference, and for implementability as a speed-independent circuit) and asynchronous logic can be automatically synthesised.