Communicating sequential processes
Communicating sequential processes
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Practical Asynchronous Controller Design
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A high-performance asynchronous SCSI controller
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Programming Approach to the Design of Asynchronous Logic Blocks
Concurrency and Hardware Design, Advances in Petri Nets
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
An Analysis of Reshuffled Handshaking Expansions
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A region-based theory for state assignment in speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
Verification and implementation of delay-insensitive processes in restrictive environments
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
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Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications.