Communicating sequential processes
Communicating sequential processes
Supervisory control of a class of discrete event processes
SIAM Journal on Control and Optimization
Proceedings of the Fourth Annual Symposium on Logic in computer science
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Delay-insensitive circuits: an algebraic approach to their design
CONCUR '90 Proceedings on Theories of concurrency : unification and extension: unification and extension
Acta Informatica
Delay-insensitive interface specification and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Practical Asynchronous Controller Design
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A high-performance asynchronous SCSI controller
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Building Finite Automata from DI Specifications
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Analysis and Applications of the XDI model
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Environment Synthesis for Compositional Model Checking
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Supervisor Reduction for Discrete-Event Systems
Discrete Event Dynamic Systems
Proceedings of the 41st annual Design Automation Conference
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Controllable Delay-Insensitive Processes
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition must be acknowledged before another one is propagated along the same wire. The environment may guarantee, however, to interact with the module in an even more restrictive way. It is worthwhile taking this into account when synthesising the module because it may allow for a cheaper, faster implementation. The concept of restriction has been built into our translation tool, di2pn (to help in synthesis), and our analysis tool, diana (to perform equivalence and refinement checking). Formally, DI-Algebra is equipped with a new operator that weakens the specification of a module by taking its environment into account. This operator is a useful instance of divergence extension, a concept introduced by Mallon. Divergence extension in general, and restriction and alternation in particular, can be represented with the parallel composition operator and so are amenable to algebraic reasoning.