Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation

Authors:
Hemangee Kapoor;Mark Josephs
Affiliations:
Dhirubhai Ambani Institute of Information and Communication Technology;Centre for Concurrent Systems and VLSI
Venue:
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Year:
2005

Citing 0
Cited 2

Verification and implementation of delay-insensitive processes in restrictive environments

Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments

Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)

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Abstract

Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.