Communicating sequential processes
Communicating sequential processes
Fairness
Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Modular verification of asynchronous networks
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Communication and concurrency
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Handbook of theoretical computer science (vol. B)
Distributed computing: models and methods
Handbook of theoretical computer science (vol. B)
Relative liveness: from intuition to automated verification
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A formal approach to designing delay-insensitive circuits
Distributed Computing
Relative Liveness: From Intuition to Automated Verification
Formal Methods in System Design
Relative liveness: from intuition to automated verification
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Submodule construction for extended state machine models
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
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We point out deficiencies of previous treatments of liveness. We define a new liveness condition in two forms: one based on finite trace theory and the other on automata. We prove the equivalence of these two forms. We introduce a safety condition and derive modular and hierarchical verification theorems for both safety and liveness. Finally, we give an algorithm for verifying liveness.