Communicating sequential processes
Communicating sequential processes
Fairness
Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Modular verification of asynchronous networks
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Communication and concurrency
Handbook of theoretical computer science (vol. B)
Distributed computing: models and methods
Handbook of theoretical computer science (vol. B)
Acta Informatica
A Formal Approach to Hardware Design
A Formal Approach to Hardware Design
Relative liveness: from intuition to automated verification
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
A formal approach to designing delay-insensitive circuits
Distributed Computing
| Hi-index | 0.00 |
We define a new liveness condition for asynchronous circuits.Although finitary (finite-execution) descriptions are not powerfulenough to express general liveness properties, those livenessproperties needed in practice appear to be related in a unique mannerto finitary descriptions. Our liveness condition exploits thisobservation and is defined directly on finitary descriptions, in twoforms: one on finite trace structures and the other on finiteautomata. We prove the equivalence of these two forms. We alsointroduce a safety condition and derive theorems for the modular andhierarchical verification theorems of both safety and liveness.Finally, we give an algorithm for verifying our liveness condition.