Modeling shared variables in VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Debugging of behavioral VHDL specifications by source level emulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Relative Liveness: From Intuition to Automated Verification
Formal Methods in System Design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic Verification of Asynchronous Circuits
IEEE Design & Test
A Light-Weight Framework for Hardware Verification
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Deductive Verification of Modular Systems
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
The priority queue as an example of hardware/software codesign
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
A rigorous environment for development of concurrent systems
Nordic Journal of Computing
Designing combinational circuits with list homomorphisms
Journal of Computational Methods in Sciences and Engineering - Selected papers from the International Conference on Computer Science,Software Engineering, Information Technology, e-Business, and Applications, 2003
A logic to specify and verify synchronous transitions
IW-FM'99 Proceedings of the 3rd Irish conference on Formal Methods
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