Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Tentative steps toward a development method for interfering programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
A Formal Approach to Hardware Design
A Formal Approach to Hardware Design
Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Temporal Verification Diagrams
TACS '94 Proceedings of the International Conference on Theoretical Aspects of Computer Software
Hierarchical Verification Using Verification Diagrams
ASIAN '96 Proceedings of the Second Asian Computing Science Conference on Concurrency and Parallelism, Programming, Networking, and Security
Assumption/Guarantee Specifications in Linear-Time Temporal Logic (Extended Abstract)
TAPSOFT '95 Proceedings of the 6th International Joint Conference CAAP/FASE on Theory and Practice of Software Development
Lazy Compositional Verification
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Hierarchical Development of Cncurrent Systems in a Temporal Logic Framework
Seminar on Concurrency, Carnegie-Mellon University
Generalized Temporal Verification Diagrams
Proceedings of the 15th Conference on Foundations of Software Technology and Theoretical Computer Science
STeP: Deductive-Algorithmic Verification of Reactive and Real-Time Systems
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Deductive Verification of Real-Time Systems Using STeP
ARTS '97 Proceedings of the 4th International AMAST Workshop on Real-Time Systems and Concurrent and Distributed Software: Transformation-Based Reactive Systems Development
Temporal Verification of Simulation and Refinement
A Decade of Concurrency, Reflections and Perspectives, REX School/Symposium
Compositional Verification of Reactive and Real-time Systems
Compositional Verification of Reactive and Real-time Systems
STeP: The Stanford Temporal Prover (Educational Release) User''s Manual
STeP: The Stanford Temporal Prover (Educational Release) User''s Manual
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Proofs of Networks of Processes
IEEE Transactions on Software Engineering
The Influence of Software Module Systems on Modular Verification
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Communication and Parallelism Introduction and Elimination in Imperative Concurrent Programs
SAS '01 Proceedings of the 8th International Symposium on Static Analysis
Automated compositional proofs for real-time systems
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
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Effective verification methods, both deductive and algorithmic, exist for the verification of global system properties. In this paper, we introduce a formal framework for the modular description and verification of parameterized fair transition systems. The framework allows us to apply existing global verification methods, such as verification rules and diagrams, in a modular setting. Transition systems and transition modules can be described by recursive module expressions, allowing the description of hierarchical systems of unbounded depth. Apart from the usual parallel composition, hiding and renaming operations, our module description language provides constructs to augment and restrict the module interface, capablilities that are essential for recursive descriptions. We present proof rules for property inheritance between modules. Finally, module abstraction and induction allow the verification of recursively defined systems. Our approach is illustrated with a recursively defined arbiter for which we verify mutual exclusion and eventual access.