ACM Transactions on Programming Languages and Systems (TOPLAS)
An old-fashioned recipe for real time
ACM Transactions on Programming Languages and Systems (TOPLAS)
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
Relative Liveness: From Intuition to Automated Verification
Formal Methods in System Design
Checking Combinational Equivalence of Speed-Independent Circuits
Formal Methods in System Design
BDD-Nodes Can Be More Expressive
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Input/Output Compatibility of Reactive Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Deductive Verification of Modular Systems
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Information and Computation
Timed I/O Automata: A Mathematical Framework for Modeling and Analyzing Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Metrics for labelled Markov processes
Theoretical Computer Science - Logic, semantics and theory of programming
The inhibition spectrum and the achievement of causal consistency
Distributed Computing
Compositional State Space Reduction Using Untangled Actions
Electronic Notes in Theoretical Computer Science (ENTCS)
Refinement preserving approximations for the design and verification of heterogeneous systems
Formal Methods in System Design
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Automated interface refinement for compositional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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