Proceedings of the Fourth Annual Symposium on Logic in computer science
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Context constraints for compositional reachability analysis
ACM Transactions on Software Engineering and Methodology (TOSEM)
Checking safety properties using compositional reachability analysis
ACM Transactions on Software Engineering and Methodology (TOSEM)
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Compositional State Space Generation from Lotos Programs
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Interface Theories for Component-Based Design
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Component Verification with Automatically Generated Assumptions
Automated Software Engineering
Breaking up is hard to do: an investigation of decomposition for assume-guarantee reasoning
Proceedings of the 2006 international symposium on Software testing and analysis
Refining interface alphabets for compositional verification
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Learning assumptions for compositional verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Refined interfaces for compositional verification
FORTE'06 Proceedings of the 26th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Automated assume-guarantee reasoning for simulation conformance
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic compositional verification by learning assumptions
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Learning-based symbolic assume-guarantee reasoning with automatic decomposition
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information and Software Technology
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
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Compositional verification is essential for verifying large systems. However, approximate environments are needed when verifying the constituent modules in a system. Effective compositional verification requires finding a simple but accurate overapproximate environment for each module. Otherwise, many verification failures may be produced, therefore incurring high computational penalty for distinguishing the false failures from the real ones. This paper presents an automated method to refine the state space of each module within an overapproximate environment. This method is sound as long as an overapproximate environment is found for each module at the beginning of the verification process, and it has less restrictions on system partitioning. It is also coupled with several state-space reduction techniques for better results. Experiments of this method on several large asynchronous designs show promising results.