Proceedings of the Fourth Annual Symposium on Logic in computer science
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Context constraints for compositional reachability analysis
ACM Transactions on Software Engineering and Methodology (TOSEM)
Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Checking safety properties using compositional reachability analysis
ACM Transactions on Software Engineering and Methodology (TOSEM)
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Compositional State Space Generation from Lotos Programs
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Compositional Reasoning in Model Checking
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Component Verification with Automatically Generated Assumptions
Automated Software Engineering
Automated Assume-Guarantee Reasoning by Abstraction Refinement
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Automated interface refinement for compositional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Learning assumptions for compositional verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Automatic abstraction for verification of cyber-physical systems
Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical Systems
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated assume-guarantee reasoning for simulation conformance
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic compositional verification by learning assumptions
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Learning-based symbolic assume-guarantee reasoning with automatic decomposition
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of timed circuits with failure-directed abstractions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a compositional minimization approach with efficient state space reductions for verifying non-trivial asynchronous designs. These reductions can result in a reduced model that contains the exact same set of observably equivalent behavior in the original model, therefore no false counter-examples result from the verification of the reduced model. This approach allows designs that cannot be handled monolithically or with partial-order reduction to be verified without difficulty. The experimental results show significant scale-up of the compositional minimization approach using these reductions on a number of large asynchronous designs.