Formal analysis and verification of a communication protocol
ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Hi-index | 0.03 |
This paper presents a method to address state explosion in timed-circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is analyzed. An algorithm is also shown to examine the abstract error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure-directed abstractions as applied to several large timed-circuit designs.