Tentative steps toward a development method for interfering programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Context constraints for compositional reachability analysis
ACM Transactions on Software Engineering and Methodology (TOSEM)
Abstract interpretation of reactive systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Compositional State Space Generation from Lotos Programs
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Compositional Minimization of Finite State Systems
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
STARI: A Case Study in Compositional and Hierarchical Timing Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Assumption Generation for Software Component Verification
Proceedings of the 17th IEEE international conference on Automated software engineering
Self-Timed FIFO: An Exercise in Compiling Programs with VLSI Circuits
Self-Timed FIFO: An Exercise in Compiling Programs with VLSI Circuits
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Proof-guided underapproximation-widening for multi-process systems
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proofs of Networks of Processes
IEEE Transactions on Software Engineering
Learning to divide and conquer: applying the L* algorithm to automate assume-guarantee reasoning
Formal Methods in System Design
Automated interface refinement for compositional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Learning assumptions for compositional verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Automated assume-guarantee reasoning for simulation conformance
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic compositional verification by learning assumptions
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of timed circuits with failure-directed abstractions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
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Compositional verification is essential to address state explosion in model checking. Traditionally, an over-approximate context is needed for each individual component in a system for sound verification. This may cause state explosion for the intermediate results as well as inefficiency for abstraction refinement. This paper presents an opposite approach, a compositional reachability method, which constructs the state space of each component from an under-approximate context gradually until a counter-example is found or a fixpoint in state space is reached. This method has an additional advantage in that counter-examples, if there are any, can be found much earlier, thus leading to faster verification. Furthermore, this modular verification framework does not require complex compositional reasoning rules. The experimental results indicate that this method is promising.