Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Analysis and identification of speed-independent circuits on an event model
Formal Methods in System Design - Special issue on designing correct circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Checking Combinational Equivalence of Speed-Independent Circuits
Formal Methods in System Design
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.