Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Kin: a high performance asynchronous processor architecture
ICS '98 Proceedings of the 12th international conference on Supercomputing
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Logic Synthesis and Verification
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
Computer
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes
IEEE Transactions on Computers
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Static Scheduling of Instructions on Micronet-based Asynchronous Processors
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A New Methodology for the Design of Asynchronous Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
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TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.