Automatic synthesis of asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Synthesis and verification of asynchronous circuits from graphical specifications
Synthesis and verification of asynchronous circuits from graphical specifications
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
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We propose a verification method of the complete state coding property for signal transition graph specifications with single cycle signals. We also propose an optimized logic synthesis method for generating speed-independent circuits without the state graph representation. We use a circuit model for each non-input signal, which consists of a C-element and AND-gates. The resulting circuit is optimized by extracting the literals. We introduce semi-lock, full-lock, and associate-lock relations to generate circuits even though the lock graph by the full-lock relation is disconnected. Our method has polynomial complexity. We compare experimentally our method with other methods, and get better or equal results.