Communications of the ACM
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Hazards, Critical Races, and Metastability
IEEE Transactions on Computers
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
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This paper discusses a new design methodology for asynchronous digital circuits. The methodology is based on an event driven scheme and follows the double-rail logic handshake protocol. A new logic gate, called the Universal Gate, is designed; this is the basic building block of the methodology. It is shown that the methodology, is completely delay insensitive. As an example, the Shift Multiplier is implemented.