Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
The essence of logic circuits
Communications of the ACM
Exact two-level minimization of hazard-free logic with multiple-input changes
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
A State Variable Assignment Method for Asynchronous Sequential Switching Circuits
Journal of the ACM (JACM)
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Introduction to VLSI Systems
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Asynchronous Embryonics with Reconfiguration
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
A New Methodology for the Design of Asynchronous Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
The Partition Method for the Order - Insensitivity in a Synchronous Distributed Systems
ISCC '00 Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000)
Model-based fault detection in context-aware adaptive applications
Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of software engineering
Brief paper: Model matching inclusion for input/state asynchronous sequential machines
Automatica (Journal of IFAC)
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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The various modes of failure of asynchronous sequential logic circuits due to timing problems are considered.These are hazards, critical races and metastable states. It is shown that there is a mechanism common to all forms of hazards and to metastable states. A similar mechanism, with added complications, is shown to characterize critical races. Means for defeating various types of hazards and critical races through the use of one-sided delay constraints are introduced. A method is described for determining from a flow table situations in which metastable states may be entered. A circuit technique is presented for extending a previously known technique for defeating metastability problems in self-timed systems. It is shown that the use of simulation for verifying the correctness of a circuit with given bounds on the branch delays cannot be relied upon to expose all timing problems. An example is presented that refutes a plausible conjecture that replacing pure delays with inertial delays can never introduce, but only eliminate glitches.