Communications of the ACM
Four State Asynchronous Architectures
IEEE Transactions on Computers
Digital design: principles and practices (2nd ed.)
Digital design: principles and practices (2nd ed.)
Hazards, Critical Races, and Metastability
IEEE Transactions on Computers
Field Programmable Processor Arrays
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
AMULET3: A 100 MIPS Asynchronous Embedded Processor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
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As embryonic arrays take inspiration from nature they display biological properties, namely complex structure and fault-tolerance. However, hardware implementations have yet to take advantage of a further biological feature at a fundamental level; asynchronous operation. Scalability and reliability are seen as two areas in which embryonic arrays could benefit from asynchronous design. This paper builds upon a previous asynchronous embryonic architecture simulation. The addition of a two-fold reconfiguration strategy that provides fault-tolerance is detailed. The simulation's design is similar to that of a macromodule library that has been implemented using Xilinx Virtex FPGAs, bringing the possibility of truly asynchronous embryonic circuits a step closer.