Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
Compiling the language Balsa to delay insensitive hardware
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Asynchronous System on Chip Interconnect
Asynchronous System on Chip Interconnect
The Design and Evaluation of an Asynchronous Microprocessor
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Macrocell Interconnect using MARBLE
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The ARM9 Family - High Performance Microprocessors for Embedded Applications
ICCD '98 Proceedings of the International Conference on Computer Design
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Asynchronous Embryonics with Reconfiguration
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Single-track asynchronous pipeline controller design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
Asynchronous ARM processor employing an adaptive pipeline architecture
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Hi-index | 0.00 |
AMULET3 is a 32-bit asynchronous processor core that is fully instruction set compatible with the clocked ARM cores. It represents the culmination of ten years of research and development into asynchronous processor design at the University of Manchester, and is the first step into commercial use for this technology. AMULET3 shows that asynchronous technology is commercially viable, and is competitive in terms of performance, area and power-efficiency with clocked design. In addition, asynchronous design offers significant advantages in terms of reduced electromagnetic interference and unique power management capabilities.