A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs

  • Authors:
  • Cesar Ortega;Andrew M. Tyrell

  • Affiliations:
  • -;-

  • Venue:
  • ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
  • Year:
  • 2000

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Abstract

This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex® FPGA from Xilinx™. The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a look-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.